This processor implements the RV32I instruction set and executes all instructions in a single clock cycle. The core consists of various interconnected modules that work together to fetch, decode, execute, and store instructions.

🧩 Module Descriptions:

Program Counter (PC): Holds the address of the current instruction. Updated every clock cycle.

Instruction Memory: Stores the machine code instructions to be executed.

Register File: Contains 32 general-purpose 32-bit registers. Supports two reads and one write per cycle.

ALU (Arithmetic Logic Unit): Executes arithmetic and logical operations based on control signals.

Control Unit: Generates control signals (RegWrite, ALUSrc, MemWrite, PCSrc, etc.) based on the opcode and funct fields.

Sign Extend: Extends immediate values to 32 bits for operations.

Data Memory: Used for lw and sw instructions to load/store data from/to memory.

Adders & Multiplexers: Used for PC update logic and data path selection.

ALU Control & Main Decoder: Further decodes instructions to generate the correct ALU operations.

🔄 Data Path Summary:

Instruction Fetch from memory using PC.

Instruction Decode using Register File and Control Unit.

Execution through the ALU, using control logic and extended immediates.

Memory Access if needed (load/store).

Write Back to the Register File.